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QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
FEATURES:
- - - - - - - - JEDEC compatible LVTTL level 10 low skew clock outputs Clock input is 5V tolerant Pinout and function compatible with QS5807 25 on-chip resistors available for low noise Input hysteresis for better noise margin Guaranteed low skew < 0.5ns (max.) between outputs: Available in QSOP and SOIC packages
QS532807
DESCRIPTION:
The QS532807 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532807 offers ten non-inverting outputs. Designed in IDT's proprietary QCMOS process, these devices provide low propagation delay buffering with less than 0.5ns on-chip skew. The QS532807 has on-chip series termination resistors for lower noise clock signals. The QS532807 series resistor version is recommended for driving unterminated lines with capacitive loading and other noise sensitive clock distribution circuits. These clock buffer products are designed for use in high-performance workstations, embedded and personal computing systems. Several devices can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks.
FUNCTIONAL BLOCK DIAGRAM
O1 O2 O3 O4 O5 IN O6 O7 O8 O9 O 10
INDUSTRIAL TEMPERATURE RANGE
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c 2001 Integrated Device Technology, Inc.
OCTOBER 2001
DSC - 5848/1
QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
IN G ND O1 VCC O2 G ND O3 VCC O4 G ND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 SO 20-2 16 SO 20-8 15 14 13 12 11 VCC O 10 O9 G ND O8 VCC O7 G ND O6 O5
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) VAC IOUT TSTG TJ Description Supply Voltage to Ground DC Output Voltage VOUT DC Input Voltage VIN AC Input Voltage (pulse width 20ns) DC Output Current VIN < 0 DC Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
(1) Unit V V V V mA mA C C
Max. - 0.5 to +4.6 - 0.5 to VCC+0.5 - 0.5 to +7 -3 -20 120 - 65 to +150 150
QSOP/ SOIC TOP VIEW
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc Terminals. 3. All terminals except Vcc.
CAPACITANCE
QSOP Pins CIN Typ. 3
(TA = +25OC, f = 1.0MHz, VIN = 0V)
SOIC 6 Typ. 5 Max. (1) 7 Unit pF Max. (1)
NOTE: 1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names IN Ox I/O I O Description Clock Input Clock Outputs
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QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 3.3V 0.3V
Symbol VIH VIL VIC VOH Parameter Input HIGH Voltage Input LOW Voltage Clamp Diode Voltage (3) Output HIGH Voltage Test Conditions Guaranteed Logic HIGH for All Inputs Guaranteed Logic LOW for All Inputs Vcc = Min., IIN = -18mA Vcc = Min., IOH = -100A Vcc = Min., IOH = -8mA Vcc = Min., IOL = 100A VOL IIN IOFF IOS IODH IODL VT ROUT Output LOW Voltage Input Leakage Current Input Power Off Leakage Short Circuit Current Output HIGH Current Output LOW Current Input Hysteresis Output Resistance (4)
(2,3)
Min. 2 -0.5 -- Vcc - 0.2 2.4 -- -- -- -- --
Typ.(1) 1.7 -- -0.7 -- -- -- -- -- -- --
Max. 5.5 0.8 -1.2 -- -- 0.2 0.4 0.5 1 1 --
Unit V V V V
Vcc = Min., IOL = 6mA Vcc = Min., IOL = 8mA Vcc = Max., VIN = VCC or GND Vcc = 0V, VIN = VCC or GND Vcc = Max., VOUT = GND Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V VTLH - VTHL for All Inputs Vcc = Min., IOL = 12mA
V A A mA mA mA V
-60 -50
50 -- --
-195 -80
112 0.2 28
-200
200 -- --
NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than one output should be used to test this high power condition. Duration is less than one second. 3. Guaranteed by design but not tested. 4. Output resistance represents the total output impedance of the logic device and includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICC ICCD IC Parameter Quiescent Power Supply Current Supply Current per Input HIGH Dynamic Power Supply Current per Output (1) Total Power Supply Current Examples
(1,3)
Test Conditions VCC = Max., VIN = GND or Vcc VCC = Max., VIN = 3V Input toggling at 50% duty cycle VCC = Max., outputs Enabled VCC = Max., Input at 50% duty cycle fI = 10MHz VCC = Max., Input at 50% duty cycle fI = 2.5MHz VIN = GND or Vcc
Typ. (2) 0.01 0.1 60 6
Max. 100 30 90 10
Unit A A A/MHz mA
VIN = GND or Vcc
1.5
3
NOTES: 1. Guaranteed by design but not tested. CL = 0pF. 2. Typical values are for reference only. Conditions are VCC = 3.3V, TA = 25C. 3. IC = ICC + (ICC)(DH)(NT) + ICCD (fO)(NO) where: DH = Input Duty Cycle NT = Number of TTL HIGH inputs at DH (one) fO = Output Frequency NO = Number of outputs at fO (ten)
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QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40C to +85C, VCC = 3.3V 0.3V CLOAD = 50pF (no resistor)
Symbol tSK(01) tSK(P) tSK(T) tPLH tPHL tR tF Parameter (1) Skew between all outputs, same transition Pulse Skew; skew between opposite transitions of the same output (tPHL - tPLH) Part-to-part skew (2) Propagation Delay (3) IN to Ox Output Rise Time, 0.8V to 2V Output Fall Time, 2V to 0.8V Min. -- -- -- 1.5 -- -- Max. 0.5 0.5 1 5.2 2 2 Unit
ns ns ns ns ns ns
NOTES: 1. Skew parameters are guaranteed across temperature range, but not tested. 2. tSK(T) only applies to devices of the same transition, part type, temperature, power supply voltage, loading, and package. 3. The propagation delay range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delays do not imply limit skew.
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QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
VCC V IN Pulse Generator 50 DU T VOUT
50pF
Pulse generator for all puls es: f 1.0M Hz; tF 2.5ns; tR 2.5ns
PROPAGATION DELAY
3V
PULSE SKEW -- tSK(P)
3V
INPUT
1.5V 0V
INPU T
1.5V 0V
tPLH
tPH L tPLH VOH
tPHL
VOH
1.5V
OUTPUT
2V
1.5V
OUTPUT
0.8V VOL tR tF
VOL
tSK(p) = tPHL - tPLHL
OUTPUT SKEW -- tSK(O1)
3V
PART-TO-PART SKEW -- tSK(T)
3V
INPUT
tPHL1
1.5V 0V
INPU T
tPHL1
1.5V 0V tPLH1
tPLH1
VOH VOH PART 1 O UTPUT
1.5V
OUTPUT 1
1.5V
VOL VOL
tSK(01) tSK(0 1) tSK(t) tSK(t)
VOH
1.5V
VOH
1.5V
PART 2 O UTPUT
OUTPUT 2
VOL VOL
tPLH2 tPHL2 tPLH2 tPHL2
tSK(01) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tSK(t) = tPLH2 - tPLH1 or tPHL2 - tPHL1
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QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
QS XXXX Device Type X Package
SO Q
Small Outline IC (300 mil) (SO20-2) Quarter-size Small Outline Package (SO20-8)
532807
Guaranteed Low Skew CMOS Clock Driver/Buffer
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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